1. Field of the Invention The present invention relates to a process for producing a silicon wafer, which is capable of highly flattening, without performing a flattening process by machine polishing such as grinding, lapping, etc.
Priority is claimed on Japanese Patent Application No. 2005-236255, filed Aug. 17, 2005, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, a production process of a semiconductor silicon wafer consists of chamfering, machine polishing such as lapping and grinding, etching, mirror finishing (polishing), and washing of a wafer which is obtained by cutting a pulled silicon single crystal ingot and slicing, thereby producing a wafer with high flatness.
In the conventional method, a wafer on which etching is finished is subjected to a mirror finishing process so as to be mirror-finished, however, the flatness between the top surface and the bottom surface of the wafer after being etched is not controlled when a flattening process such as grinding, lapping, etc. is finished. Moreover, desirable surface coarseness has not been obtained, and hence it is necessary to remove a large amount of silicon in thickness during the mirror-finishing process in order to improve the wafer flatness and wafer surface coarseness, thereby applying a large load to the mirror-finishing process.
Then, as a process for producing a silicon wafer which is capable of removing efficiently the process-strained layer generated by the machine polishing, while securing the flatness, a process is disclosed in for example Japanese Unexamined Patent Application, First Publication No. H11-135464(claim 1, FIG. 1), as shown in FIG. 16, the process comprising step 1 of slicing a silicon single crystal, step 2 of chamfering the end surface of the sliced wafer, step 3 of flattening by planar grinding or lapping at least a top surface of a wafer which is obtained by slicing a semiconductor ingot, step 4 of etching by spin-etching the top surface of the wafer which is flattened, and step 5 of grinding the top surface of the etched wafer to form a mirror-surface.
However, the method disclosed in Japanese Unexamined Patent Application, First Publication No. H11-135464 generates grinding-scratches which are caused by wafer-holding upon being ground by machine polishing during the flattening process, and waviness on the surface of the wafer, and as a result, it is necessary to remove a large amount of silicon in thickness during the mirror-finishing process in order to remove the grinding-scratches and waviness, thereby also applying a large load to the mirror-finishing process.
Thus, it is an object of the present invention to provide a process for producing a silicon wafer which is capable of performing a high level of flattening, without performing any flattening process using machine polishing such as grinding and lapping, which has been indispensable for the conventional manufacturing process, and of increasing productivity.